Analog-to-digital converters (ADCs) are widely used to process electrical signals in many electronic applications. An integrated circuit ADC typically accepts an analog input voltage signal and converts the signal into a digital form as the output. A modern digital communication system, such as for a cellular telephone base station, for example, may often require an ADC with a high resolution of greater than 12 bits, a bandwidth greater than 200 MHz, and low power consumption and low distortion for improved overall system performance.
A pipelined ADC includes a series of subconverter stages with each stage including a flash analog-to-digital converter, a digital-to-analog converter (DAC) and an interstage amplifier connecting the DAC to an adjacent stage. The last stage typically includes only a flash ADC. A multi-step ADC may include one or more similar subconverter stages which are sequentially reused in generating the digital output signal.
The analog signal which is input to an ADC may have different ranges. For example, for communications applications, the analog input signal may cover only a portion of the range of the ADC. In other words, a large portion of the available resolution of the ADC may be wasted. To address such a shortcoming, a prior art circuit 10 as shown in FIG. 1 may be used which includes an integrated circuit programmable gain amplifier (PGA) 11 connected to the input of an ADC chip 12 to thereby control the level of the input analog signal for full resolution by the ADC. As shown, the PGA 11 is also typically a separate integrated circuit from the integrated circuit ADC 12. Accordingly, the overall circuit 10 is relatively large. U.S. Pat. No. 5,144,311 to Buhler et al. also discloses a similar circuit including a portion which comprises an ADC with an optional PGA for adjusting the input level to the ADC.
The gain of a typical PGA 11 as used in the illustrated prior art circuit 10 is either voltage-controlled, or controlled by a digital word including gain setting bits. Of course, such a typical PGA 11 has a limited gain-bandwidth product. Accordingly, as shown in the plots 14, 16 of FIGS. 2 and 3, respectively, the prior art circuit 10 may have a relatively slow response time to change the gain setting. The gain change may be slow as compared to the conversion cycle time of the ADC 12. In other words, the gain cannot be quickly changed, and accuracy is therefore sacrificed.